An input buffer included in a conventional SRAM will be described with reference to FIG. 1.
The input buffer serves as a circuit for converting a signal having a TTL (Transistor Transistor Logic) level to a signal having a CMOS (Complementary MOS) level. The input buffer comprises CMOS transistors. Described specifically, the input buffer comprises a PMOS transistor (hereinafter also "PMOS") 1 whose source is electrically connected to a power source potential VCC, an NMOS transistor (hereinafter also "NMOS") 2 whose source is electrically connected to a ground potential VSS and an inverter 3. The signal having the TTL level is input to each of the gates of the PMOS 1 and the NMOS 2.
FIG. 2(a) shows the voltages of a signal having a TTL level, which is represented as an input signal. FIG. 2(b) shows the voltages of a signal having a CMOS level, which is represented as an output signal.
The operation of the input buffer shown in FIG. 1 will now be described with reference to FIGS. 2(a) and 2(b).
When a signal having a TTL level of 0.8 V is first input to the input buffer as an input signal having an "L" level, the PMOS 1 is turned on and the NMOS 2 is turned off. As a result, the level of a signal output from the input buffer through the inverter 3 is brought to the ground potential VSS (0 V), for example.
When a signal having a TTL level of 2.2 V is input to the input buffer as an input signal having an "H" level, the NMOS 2 is brought into a conducting state. Thus, the level of a signal output from the input buffer through the inverter 3 is brought to a power source potential VCC (5 V), for example. As a result, a signal having the TTL level is converted to a signal having the CMOS level as shown in FIGS. 2(a) and 2(b).